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A statement is an complete instruction to the make processor.

Syntax

    Commands Description
    Assignment identifier = value
    Inference .sourceextension.targetextension:
    command ...
    Target target: srcfile { depfile }...

Example

    #sample makefile
    
    #-----------------------------
    INCLUDES = global.h ppsup.h
    LIBS = global.lib ppsup.lib
    #-----------------------------
    .c.obj:
        cl /c $*.c
    
    .obj.lib:
        lib /out $*.lib $*.obj
    
    .obj.exe:
        link $*.obj $(LIBS)
    
    #-----------------------------
    all:        pp.exe
    
    #-----------------------------
    pp.exe:     pp.obj $(LIBS)
    pp.obj:     pp.c pp.h $(INCLUDES)
    
    #-----------------------------
    ppsup.lib:  ppexpr.obj symtab.obj
    ppexpr.obj: ppexpr.c $(INCLUDES)
    symtab.obj: symtab.c $(INCLUDES)
    
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Last Modified: Sun Sep 04 14:56:00 EDT 2005